(1) Field of the Invention
The present invention relates to a packet processing device, and more particularly, to a packet processing device for processing packets in conjunction with a communication network.
(2) Description of the Related Art
In recent years, computers and various other information processing devices are interconnected by networks, expanding the scale of communication systems. Among networks constructing communication systems, IP (Internet Protocol) network is currently the most prevalent one. IP is a connectionless protocol corresponding to the Network layer.
Packet processing for such an IP network involves packet filtering for restricting communications through the network, in addition to processes necessary for relaying packets, such as checksum calculation for packet headers, search of destination table, and updating of packet headers.
These processes are too complicated to be implemented by dedicated hardware, and also since the procedure is subject to change because of the revision of the protocol itself, conventionally the processes were usually implemented by software with the use of a processor.
For example, a processor and a memory are connected by a bus, and the program stored in the memory is executed by the processor to process packets.
In such packet processing, however, memory access for reading/writing data from/into the memory increases overhead, and also due to the limitations of access bandwidth of the memory itself, it was difficult to speed up the packet processing.
In view of the circumstances, Japanese Unexamined Patent Publication No. 2000-349816 proposes a series connection of packet processors each including a packet access register for directly reading in packet data.
With this arrangement, the result of packet processing by a packet processor of a preceding stage is input to the succeeding-stage packet processor, so that individual packets are subjected to a pipeline process.
By constructing such a pipeline processing system, it is possible to process packets more efficiently than the conventional arrangement wherein a processor and a memory are connected to each other.
Even with the second-mentioned conventional technique of carrying out the packet processing separately by serially connected processors having packet input-output sections, a problem arises in that the performance cannot be enhanced up to a level corresponding to the number of the processors connected.
Where the packet processing is performed by separate processors, it is necessary that an intermediary processing status should be handed over from a preceding-stage processor to a succeeding-stage processor, and conventionally, the necessary information is handed over as parameters. Thus, the preceding-stage processor is required to generate parameters while the succeeding-stage processor is required to interpret and recognize the parameters.
For example, in cases where packets are processed separately according to their protocol types, the process of analyzing packet headers to identify the protocol types and the process to be executed with respect to a specific protocol are assigned to separate processors.
As a consequence, the preceding-stage processor needs to convert values indicative of the identified protocol to parameters before transmitting the results to the succeeding stage, and the succeeding-stage processor needs to make a comparison to determine whether or not the protocol indicated by the parameters is the one to be processed thereby.
Processing overhead like this exerts a greater influence upon the throughput as the required throughput increases. For example, in the case where a process involves five steps, the overhead is 5% if the allowable processing time of each processor is 100 steps in terms of the number of instruction steps, but reaches 50% if the allowable processing time becomes 10 steps. Where an even higher throughput is required, the overhead accounts for nearly all of the process performed.
Accordingly, even if processors are arranged to constitute a pipeline structure and a process to be executed is divided into a plurality of processing stages to restrain the processing load on each processor, the overhead can still increase as mentioned above so long as the handover of information between processors is performed in a generalized form using parameters, as in the conventional technique.